This invention relates to circuitry associated with a sample and hold circuit, particularly to a droop compensation circuit for preventing a sampled signal voltage from changing with time.
Sample and hold circuits which momentarily connect a capacitor to a signal, typically through an amplifier, until the capacitor is charged to the level of that signal and thereafter disconnect the capacitor to store that level by retaining the charge on the capacitor are commonly known and used in many applications. One problem encountered with such circuits is that over a period of time the charge of the capacitor increases or decreases as a result of its being used to provide the sampled level to a subsequent device. Typically the capacitor is connected to the input of a buffer, output amplifier whose bias current charges or discharges the capacitor, depending upon the type of amplifier device. Consequently, the sampled voltage tends to change or "droop".
One application in which such sample and hold circuits are used is in association with an oscillator to sample the oscillator output signal and employ that sample to control the oscillator amplitude. If the voltage across the storage capacitor is allowed to change then the voltage appearing at the sample and hold circuit output will be different from the actual sampled voltage by an amount equal to the magnitude of the change in voltage. At low frequencies, for example, about 10 hertz, there is a significant time delay between successive oscillator cycles, so the droop effect may become pronounced toward the end of each cycle. This produces a sawtooth waveform which, when superimposed on the oscillator sine wave output, shows up as ripple distortion in the oscillator output waveform.
Accordingly, it is desirable to employ circuitry associated with the sample and hold circuit to prevent droop from occurring.